International Journal of Engineering Technology and Scientific Innovation
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Reyhaneh Pedram, Mohammad Reza Amini

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Reyhaneh Pedram, Mohammad Reza Amini
Department of Electrical Engineering, College of Engineering, Borujerd Branch, Islamic Azad University, Borujerd, Iran

Pedram, Reyhaneh, and Mohammadreza Amini. "IMPLEMENTING A RECONFIGURABLE NEURAL BASED DEMODULATOR ON AN FPGA." IJETSI, vol. 3, no. 1, pp. 32-51,
Pedram, Reyhaneh, and Mohammadreza Amini. "IMPLEMENTING A RECONFIGURABLE NEURAL BASED DEMODULATOR ON AN FPGA." IJETSI 3, no. 1 (n.d.), 32-51.

[1] . P. Koprinkova-Hristova, V. Mladenov, and N. K. Kasabov, Artificial Neural Networks: Springer International Publishing, 2015.
[2]. L. Iliadis and C. Jayne, Engineering Applications of Neural Networks: Springer International Publishing, 2015.
[3]. S. Bassis, A. Esposito, and F. C. Morabito, Recent Advances of Neural Network Models and Applications: Springer International Publishing, 2014.
[4]. J. G. M. Oliveira, R. L. Moreno, O. d. O. Dutra, and T. C. Pimenta, "- Implementation of a reconfigurable neural network in FPGA," vol. -, pp. - 44, 2017.
[5]. F. Ortega-Zamorano, J. M. Jerez, G. Juarez, J. O. Perez, and L. Franco, "High precision FPGA implementation of neural network activation functions," in 2014 IEEE Symposium on Intelligent Embedded Systems (IES), 2014, pp. 55-60.
[6]. H. Hu, J. Huang, J. Xing, and W. Wang, "Key Issues of FPGA Implementation of Neural Networks," in 2008 Second International Symposium on Intelligent Information Technology Application, 2008, pp. 259-263.
[7]. S. Sahin, Y. Becerikli, and S. Yazici, "- Neural Network Implementation in Hardware Using FPGAs," pp. - 1112, 2006.
[8]. A. R. Omondi and J. C. Rajapakse, FPGA Implementations of Neural Networks: Springer US, 2006.
[9]. C. Thomos and G. Kalivas, "- FPGA-based architecture and implementation techniques of a lowcomplexity hybrid RAKE receiver for a DSUWB communication system," vol. - 52, pp. - 2099, 2013.
[10]. A. A. Moldovyan, N. A. Moldovyan, and N. Sklavos, "- Controlled elements for designing ciphers suitable to efficient VLSI implementation," vol. - 32, pp. - 163, 2006.
[11]. A. Banerjee and A. S. Dhar, "Novel architecture for QAM modulator- demodulator and its generalization to multicarrier modulation," vol. - 29, pp. - 357, 2005.
[12]. J. Bag, S. Roy, P. K. Dutta, and S. K. Sarkar, "Design of a DPSK Modem Using CORDIC Algorithm and Its FPGA Implementation," vol. - 60, pp. - 363, 2014.
[13]. F. Angarita, M. J. Canet, T. Sansaloni, A. Perez-Pascual, and J. Valls, "- Efficient Mapping of CORDIC Algorithm for OFDM-Based WLAN," vol. - 52, 2007.
[14]. S. W. Mondwurf, "- Versatile COFDM demodulator design based on the CORDIC-algorithm," vol. - 48, pp. - 723, 2002.
[15]. M. Amini, A. Samimi, and A. Mirzavandi, "Joint optimisation of transmission and waiting times in cognitive radio," International Journal of Electronics, vol. 103, pp. 747-764, 2016/04/02 2016.
[16]. M. Amini and A. Mirzavandi, "Phase-Type Model Spectrum Sensing for Cognitive Radios," IETE Journal of Research, vol. 0, pp. 1-7, 2015 2015.
[17]. M. R. Amini and E. Balarastaghi, "Universal Neural Network Demodulator for Software Defined Radio," International Journal of Machine Learning and Computing, vol. 1, pp. 305-310, 2011.
[18]. M. R. Amini and E. Balarastaghi, "Improving ann bfsk demodulator performance with training data sequence sent by transmitter," presented at the Machine Learning and Computing (ICMLC), 2010 Second International Conference on, Bangalore, India, 2010.
[19]. P. A. Kowalski and M. Kusy, "Sensitivity Analysis for Probabilistic Neural Network Structure Reduction," IEEE Transactions on Neural Networks and Learning Systems, vol. PP, pp. 1-14, 2017.
[20]. N. T. Dukov, "Comparative evaluation of probability density estimators for the probabilistic neural network," in 2016 XXV International Scientific Conference Electronics (ET), 2016, pp. 1-4.
[21]. C. Phaudphut, C. So-In, and W. Phusomsai, "A parallel probabilistic neural network ECG recognition architecture over GPU platforms," in 2016 13th International Joint Conference on Computer Science and Software Engineering (JCSSE), 2016, pp. 1- 7.
[22]. S. Ramakrishnan and I. M. M. El Emary, "- Classification brain MR images through a fuzzy multiwavelets based GMM and probabilistic neural networks," vol. - 46, pp. - 252, 2011.
[23]. O. Vysochyna and A. M. Salman, "Using probabilistic neural networks for diagnostics and prediction model of the router state," in 2010 International Conference on Modern Problems of Radio Engineering, Telecommunications and Computer Science (TCSET), 2010, pp. 255- 255.
[24]. S. Kala, "- Design of a software defined radio receiver using FM channelizer - A case study," vol. -, pp. - 4, 2016.
[25]. H. Arslan and H. Celebi, "- Software Defined Radio Architectures for Cognitive Radios," pp. - 144, 2007.
[26]. M. R. Amini, M. Mahdavi, and M. J. Omidi, "Analysis of a multi-user cognitive radio network considering primary users return," Computers & Electrical Engineering, vol. 53, pp. 73-88, 7// 2016.
[27]. M. R. Amini, F. Hemati, and A. Mirzavandi, "Trilateral Tradeoff of Sensing, Transmission, and Contention Times in a Multiuser Split-Phase CR Networks," IEEE Sensors Journal, vol. 15, pp. 6044-6055, 2015.
[28]. B. Dacorogna, Direct Methods in the Calculus of Variations: Springer-Verlag New York, 2008.
[29]. M. Razzaghi and H.-R. Marzban, "Direct method for variational problems via hybrid of block-pulse and chebyshev functions," Mathematical Problems in Engineering, vol. 6, pp. 85-97, 2000.

In this study a universal demodulator for BPSK, BFSK, ASK signals is presented. This demodulator is based on neural network techniques and can be developed for any kind of modulation scheme. Regardless of modulation type used by transmitters, this demodulator can detect the transmitted signal bits by passing the signal samples through a probabilistic neural network. Each modulation scheme that is best similar and matched to the incoming signal samples will be determined as a detected pattern and its corresponding bit is detected as a received bit. The demodulator has its own architecture techniques to implement via VHDL code for speed and chip area optimization.